1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a dual gate structure in which a transistor having a grooved gate structure and a transistor having a planar gate structure are provided on the same substrate, and a grooved gate and a planar gate are made in different conductivity types.
2. Related Art
Recently, semiconductor devices, especially dynamic random access memories (DRAMs), have often used a poly-metal gate structure to improve operating speeds of the devices. The poly-metal gate structure means a stacked structure of a polysilicon layer and a metal layer, in which it is easy to control impurity concentration in the polysilicon layer and which can operate at a high speed because of a combination with a low-resistance metal such as tungsten. A method for manufacturing a gate electrode employing the poly-metal gate structure is disclosed, for example, in JP-A No. 2003-163348 (D1). The method described in D1 includes: stacking an impurity-doped polysilicon layer, a silicide layer of a first refractory metal, a nitride layer of the first refractory metal and a second refractory metal layer in sequence; and heat treating the stacked layers in an integrated manner. This method, while efficiently preventing occurrence, upon heat treating, of failures such as lowered impurity concentration in the impurity-doped polysilicon layer, or diffusion of metal atoms from the refractory metal layers, provides the gate electrode having a structure in which the silicide-nitride layer of the refractory metal, which is a diffusion barrier layer, can be formed as thin as possible, so that interface resistance between the refractory metal layer and the impurity-doped polysilicon layer can be more reduced, compared to a conventional one.
Further, to improve performance and lower drive voltage of devices, a poly-metal gate structure of a dual gate type has been also employed. The dual gate structure is a structure using: a gate electrode including N-type polysilicon into which an N-type impurity (such as phosphorus (P)) is injected, for a gate electrode of an N-channel transistor; and a gate electrode including P-type polysilicon into which a P-type impurity (such as boron (B)) is injected, for a gate electrode of a P-channel transistor.
On the one hand, as devices are further miniaturized, a distance between a source and a drain is narrowed, and there arises a problem of a so-called “short channel effect” such as an increase in junction leakage current, lowering of breakdown voltage between a source and a drain, and a decrease in data holding time. For one method to solve the short channel effect, a so-called “grooved gate structure” is formed in which a groove is formed in a substrate, and in the groove, a gate electrode is formed, thereby an effective channel length can be efficiently prolonged. JP-A No. 2005-39270 (D2) discloses a device in which, especially in a memory cell portion that has been further miniaturized, the grooved gate structure is employed, and in a portion that has not been severely required to be miniaturized, such as a logic portion, a conventional, planar gate structure is employed.
There is provided a combination of the related arts described above, that is, the poly-metal gate structure configured by stacking the polysilicon layer, the ion injection layer, the silicide layer, the metal nitride layer, and the metal layer as disclosed in D1, and the dual gate structure in which the grooved gate and the planar gate are provided on one substrate, and the grooved gate and the planar gate are made in different conductivity types as disclosed in D2, are combined with each other, and thereby, it is thought, a superior device would be provided that solves defects accompanying miniaturization of devices. Then, the present inventors studied production of such devices. However, if, for reduction in processes, a polysilicon layer under a gate layer is formed in one process, dopant does not sufficiently spread in the polysilicon layer to be buried into the groove, on the grooved gate side, and it is difficult to maintain transistor characteristics because of depletion of the polysilicon in the case where the polysilicon layer providing the gate electrode is formed to have a film thickness most suitable for the planar gate. The depletion of the polysilicon in the grooved gate may be solved to some degree by increasing a dose amount, but a too much dose amount makes resistance in a gate interface high, and it is difficult to appropriately control the dose amount.
On the other hand, if the polysilicon layer is formed to have a film thickness in which the dopant sufficiently spreads in the polysilicon in the groove, an impurity different from that of the grooved gate, for example, boron, is injected to the planar gate, then there occurs a phenomenon in which boron passes through a gate insulating film, so that characteristics of a planar gate transistor can not be maintained because of variation in a threshold voltage of the transistor.
As a matter of course, the grooved gate and the planar gate are separately formed, and a polysilicon layer having a film thickness most suitable for each is formed, respectively, which solves such problems, but by just that much, processes increase, and are made cumbersome and complicated. When the grooved gate and the planar gate are made in an identical conductivity type as in D2 described above, polysilicon can be formed while dopant is injected, so that these problems do not occur.